This invention relates to a semiconductor device.
With the rapid progress of the technique for high density assembly of large scale integrated circuits (LSI), semiconductor memories have recently been used with such large capacity as 16K bits or 64K bits in the. While the large-capacity memories of this type are obtained by the use of semiconductor devices which are formed of single-channel MOS transistors, such as n-channel MOS transistors, 4K-bit or 16K-bit memories may also be formed of complementary MOS (CMOS) semiconductor devices which have conventionally been considered difficult to provide high density integration. These large-capacity memories in the field, however, are realized by reducing the size of the semiconductor devices and are greatly dependent upon improvements in the minute pattern transfer technique and not itself by improving the structure itself of the semiconductor element.
There still remains the restriction on the high density integration due to the coexistence of p- and n-channel MOS transistors inherent to the CMOS semiconductor devices for example. The gate electrodes of p- and n-channel MOS transistors of a CMOS semiconductor device, for example, are coupled by means of an aluminum interconnection layer, which, however, makes it difficult to realize multilayer interconnection. Accordingly, there is proposed a method in which the gate electrodes of the p- and n-channel MOS transistors are formed of polycrystalline layers of the same conductivity type, e.g. p-type, and these gate electrodes are coupled by means of a p-type polycrystalline silicon interconnection layer. In this case, however, an aluminum interconnection layer is required for the source and drain regions of the n-channel MOS transistor, eventually interfering with the achievement of high density integration.
Meanwhile, in a semiconductor device using an insulating substrate, such as a semiconductor device of, e.g., a silicon-on-sapphire (SOS) type, which has recently been attracting public attention, p- and n-type silicon layers can sometimes be formed in contact with each other on the insulating substrate. Further, there will be no latch-up phenomenon which will constitute a hindrance to the use of a semiconductor substrate, so that it is possible to provide a high-density LSI. In order to achieve high density integration, for example, a p-type inter-connection layer is directly connected only with the p-type silicon layer instead of coupling an aluminum interconnection layer with the p- and n-type silicon layers. In this case, however, a p-n junction formed between the p- and n-type silicon layers will possibly exert an influence upon the electrical properties of the semiconductor device.